In high voltage processes it is common to have transient latch-up. For example latch-up current may flow between adjacent high voltage pins protected by high voltage electrostatic discharge (ESD) devices or between the ESD device and internal circuitry.
In particular, in structures where there are n and p laterally spaced regions such as n-type epitaxial (n-epi) regions and p-isolation, a parasitic current path can be created through the lateral parasitic NPN formed by the n-epi regions and p-isolation to provide an n-epi to n-epi transient latchup scenario. This is, for instance found in the case of a BCD process between an NLDMOS-SCR ESD clamp and a laterally arranged PNP clamp. The lateral PNP can also be implemented in an extended voltage CMOS process to define the parasitic NPN.
FIG. 1 shows a circuit diagram of a high voltage control pin 100 and power pin 102. The control pin is protected by an NLDMOS-SCR ESD clamp 110, while the power pin is protected by a high holding voltage lateral PNP ESD clamp 112. During ESD tests the power ground node 114 is floating, which creates variable conditions on the base of the parasitic NPN 120. The NPN 120 is formed by a p-isolation ring 200 (FIG. 2) formed between n-epi regions of the two clamp structures that are separated by the p-isolation ring 200 and that define the collector and emitter of the parasitic NPN. The n-epi regions shown in FIG. 2 are provided with n-sinker epitaxial ties 202, 204.
Depending on internal circuit design and metallization routing, the latch-up current through the parasitic NPN can simply pass to ground through the ESD devices, but in many situations the current causes irreversible burnout of one or both ESD devices.
In order to provide a dual direction current path in an ESD protection circuit, a current path may be defined in the forward direction by an ESD snapback device, and in the reverse direction by a reverse biased diode. In the circuit of FIG. 1, reverse current protection is provided by means of reverse biased diodes 140, 142. These body diodes are often sufficient for the pin protection during high voltage reverse currents. However, if two clamps are placed adjacent to each other with minimum isolation rules, the total voltage between two high voltage pins may exceed the parasitic NPN turn-on voltage, especially in the case of fast transient modes e.g. due to excessive reverse path diode voltage drop.